Experiment confirms high-speed potential of STT-MRAM

5th December 2018
Posted By : Mick Elliott
Experiment confirms high-speed potential of STT-MRAM

A collaboration between Advantest and Tohoku University’s Center for Innovative Integrated Electronic Systems led by Tetsuo Endoh has successfully demonstrated operation of a high-writing-speed spin-transfer torque magnetic random access memory (STT-MRAM) using an Advantest memory test system.

In this experiment, researchers measured a 128Mb density STT-MRAM device developed by the CIES industry-academia collaborative research project "R&D of STT-MRAM aimed at developing non-volatile working memory and its manufacturing technologies” using an Advantest memory test system.

The experiment confirmed that high-speed operation of a STT-MRAM device takes 14 nanoseconds at 1.2V, which is comparable to the voltage used in conventional semiconductor integrated circuits, and at 1.3V takes 10 nanoseconds, the same as conventional SRAM.

This demonstrates the high-speed operation potential of large-capacity STT-MRAM and the effectiveness of high-speed memory performance evaluation technology, which will be indispensable for mass production of STT-MRAM.

The successful experiment was based on joint research by Advantest and the CIES Consortium, and the OPERA (Program on Open Innovation Platform with Enterprises, Research Institute and Academia) program.

Advantest and Tohoku University CIES will continue research and development activities aiming to commercialise a new STT-MRAM memory test system equipped with an external magnetic field application mechanism.

The results of this research were presented at the EEE International Electron Devices Meeting held in San Francisco.

Picture shows the result of high-speed characterisation of sub-array in the 128MB density STT-MRAM.


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