IPC compliant THT solder joint inspection

23rd June 2016
Posted By : Peter Smith
IPC compliant THT solder joint inspection

The X-ray inspection system X Line 3·D from GOEPEL electronic is designed to enable reliable inspection of THT and Pin-in-Paste solder joints in compliance with the IPC quality standard through a unique combination of 3D X-ray (AXI) and 2D AOI inspection. This level of inspection is particularly important for automotive assemblies which are subject to strict quality requirements.

Unlike simple two-dimensional X-ray inspection, 3D X-ray inspection allows evaluation of the solder penetration for THT connectors. Assemblies which are subject to the IPC norm must show a solder penetration of 50 to 75 percent at the pin, depending on the IPC class. These requirements can be assured through evaluation of the solder penetration layer by layer. The limits of X-ray technology in this particular application are, however, the requirement of circumferential wetting of pins and the wetted connecting surface (ring). As an example, according to the IPC, the circumferential wetting must be proven to be between 270° and 330°. Only the combination of two technologies can provide compliance with this standard. By using a fully integrated and automated AOI module, both circumferential wetting and wetted connecting surface can be evaluated at the solder side.

With the X Line 3·D and the AXOI technology (combined X-ray and optical inspection), maximum fault coverage at line cycle times can be achieved. By scanning image acquisition, time-efficient quality control is made possible.  Hole fill levels, pin and pad wetting, bridging and solder balls can be detected with one single system. The X Line·3D is an inspection system for the safe testing of double-sided assembled PCBs. The three-dimensional X-ray inspection covers both top and bottom sides within a continuous process. The basis of this technology is real-time multi-angle image acquisition, which allows a complete 3D capture of the assembly. Integrated reconstruction methods based on planarGT provide detailed evaluation of the PCB under test layer by layer.

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